1. Field of the Invention
This invention relates to circuits for protecting against damage to other circuits caused by electrostatic discharge.
2. Description of Related Art
Electrostatic discharge (ESD) is a well known concern when designing an integrated circuit (IC). ESD spikes coupled to an input pad of an IC can be several thousand volts and can destroy circuitry within an IC, especially field effect transistors (FETs). Accordingly, ICs frequently provide some sort of protection circuit for preventing high voltage ESD spikes applied to input pads from reaching internal devices.
One example of a prior art circuit for protecting against electrostatic discharge is shown in FIG. 1. In the example of FIG. 1, if a positive electrostatic spike is applied to input pad 12, the spike is shunted to the positive power supply terminal 14 through PN junction diode D1 so that the maximum voltage appearing at node 10 is approximately the supply voltage plus the diode drop (e.g., 0.7 volts) of diode D1. Resistor R1 connected between node 10 and input pad 12 limits the current through diode D1. If a negative spike is applied to input pad 12, the spike is shunted to ground through PN junction diode D2 so that the maximum voltage on node 10 is approximately -0.7 volts.
One problem with the circuit of FIG. 1 is that diodes D1 and D2 inject minority carrier into the substrate or region in which the diodes are formed. This may result in unwanted PNP action, NPN action, four-layer diode action, or residual charges being trapped in the substrate or region. The injected minority carriers continue to affect the operation of the IC until the charges drain off. The injection of minority carriers can also cause latch-up of devices formed in the substrate.
Another problem with the circuit of FIG. 1 is that the protection circuit generally must be connected to the supply voltage V.sub.cc in order to protect against ESD. Therefore, the protection circuit does not operate when V.sub.cc is not connected, such as when the IC is being handled out of its socket.
The above prior art approach and similar prior art approaches require one or two PN (or NP) junctions to be formed prior to a metallization step, which electrically contacts the various surface regions. However, in some technologies, forming a suitable PN (or NP) junction requires extra masking and diffusion steps. In some cases, two additional diffusions are required to form PN or NP junctions while attempting to minimize minority carrier injection into the substrate or to minimize any PNP, NPN, or four-layer diode problem.
There is a need for a circuit that protects against positive and negative ESD, that does not inject minority carriers into a substrate or region, that is simple to fabricate, that takes up little silicon surface area, and that protects against ESD even when not connected to a power supply.